HD64F3437TF16 Datasheet, PDF (547/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

At this time, the values of general registers in the CPU are undetermined. Thus these registers
should be initialized immediately after branching to the user program. Especially in the case of
the stack pointer (SP), which is used implicitly in subroutine calls, etc., the stack area used by
the user program should be specified.
There are no other changes to the initialized values of other registers.
6. Boot mode can be entered by starting from a reset after pin settings are made according to the
mode setting conditions listed in table 21.6.
In the H8/3437SF, P9₂, P9₁, and P9₀ can be used as I/O ports if boot mode selection is detected
when reset is released^*1.
Boot mode can be released by driving the reset pin low, waiting at least 20 system clock
cycles, then setting the mode pins and releasing the reset^*1.
Boot mode can also be released if a watchdog timer overflow reset occurs.
The mode pin input levels must not be changed during boot mode.
7. If the input level of a mode pin is changed during a reset (e.g., from low to high), the resultant
switch in the microcontroller’s operating mode will affect the bus control output signals (AS,
RD, and WR) and the status of ports that can be used for address output^*2.
Therefore, either set these pins so that they do not output signals during the reset, or make sure
that their output signals do not collide with other signals output the microcontroller.
Notes: *1 Mode pin input must satisfy the mode programming setup time (t_MDS = 4 states) with
respect to the reset release timing.
*2 These ports output low-level address signals if the mode pins are set to mode 1 during
the reset. In all other modes, these ports are in the high-impedance state. The bus
control output signals are high if the mode pins are set for mode 1 or 2 during the reset.
In mode 3, they are at high impedance.
RES
tMDS
MD_0, MD₁
P9₂
P9₁
P9₀
tMDS: 4t_CYC (min.)
Figure 21.10 Programming Mode Timing
518