HD64F3437TF16 Datasheet, PDF (79/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Exception
handling
request
Exception-
handling state
Program
execution state
Exception
handing
Interrupt request
SLEEP instruction
with SSBY bit set
SLEEP
instruction
Sleep mode
RES = 1
NMI, IRQ₀
to IRQ₂ or IRQ₆
Software
standby mode
Reset state
STBY = 1, RES = 0
Hardware
standby mode
Power-down state
Notes: 1. A transition to the reset state occurs when RES goes low, except when the chip
is in the hardware standby mode.
2. A transition from any state to the hardware standby mode occurs when STBY
goes low.
Figure 2.12 State Transitions
2.6.2 Program Execution State
In this state the CPU executes program instructions.
2.6.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or interrupted
and changes its normal processing flow. In interrupt exception handling, the CPU references the
stack pointer (R7) and saves the program counter and condition code register on the stack. For
further details see section 4, Exception Handling.
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