HD64F3437TF16 Datasheet, PDF (531/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

21.1.4 Input/Output Pins
Flash memory is controlled by the pins listed in table 21.2.
Table 21.2 Flash Memory Pins
Pin Name
Reset
Mode 1
Mode 0
Port 92
Port 91
Port 90
Transmit data
Receive data
Abbreviation
RES
MD₁
MD₀
P9₂
P9₁
P9₀
TxD₁
RxD₁
Input/
Output
Input
Input
Input
Input
Input
Input
Output
Input
Function
Reset
H8/3437SF operating mode setting
H8/3437SF operating mode setting
H8/3437SF operating mode setting when MD1 =
MD0 = 0
H8/3437SF operating mode setting when MD1 =
MD0 = 0
H8/3437SF operating mode setting when MD1 =
MD0 = 0
SCI1 transmit data output
SCI1 receive data input
The transmit data and receive data pins are used in boot mode.
21.1.5 Register Configuration
The flash memory is controlled by the registers listed in table 21.3.
Table 21.3 Flash Memory Registers
Name
Abbreviation R/W
Initial Value Address
Flash memory control register 1
FLMCR1
R/W^*2
H'80
H'FF80
Flash memory control register 2
FLMCR2
R/W^*2
H'00^*3
H'FF81
Erase block register 2
EBR2
R/W^*2
H'00^*3
H'FF83
Wait-state control register^*1
WSCR
R/W
H'08
H'FFC2
Notes: *1 The wait-state control register is used to control the insertion of wait states by the wait-
state controller and frequency division of clock signals for the on-chip supporting
modules by the clock pulse generator. Selection of the respective registers (or
FLMCR1, FLMCR2, and EBR2) is performed by means of the FLSHE bit in the wait
state control register (WSCR).
*2 In modes in which the on-chip flash memory is disabled, these registers cannot be
modified and return H'00 if read.
*3 Initialized to H'00 when the SWE bit is not set in FLMCR1.
502