HD64F3437TF16 Datasheet, PDF (223/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1.
Bit 5: OVIE
0
1
Description
The timer overflow interrupt request (OVI) is disabled.
The timer overflow interrupt request (OVI) is enabled.
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input (TMRI).
Bit 4: CCLR1
0
1
Bit 3: CCLR0
0
1
0
1
Description
Not cleared.
(Initial value)
Cleared on compare-match A.
Cleared on compare-match B.
Cleared on rising edge of external reset input signal.
194