HD64F3437TF16 Datasheet, PDF (644/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates
the number of cycles of each type occurring in each instruction. The total number of states
required for execution of an instruction can be calculated from these two tables as follows:
Execution states = I × S_I + J × S_J + K × S_K + L × S_L+ M × S_M + N × S_N
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A.4: I = L = 2, J = K = M = N= 0
From table A.3: S_I = 8, S_L = 3
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A.4: I = 2, J = K = 1, L = M = N = 0
From table A.3: S_I = S_J = S_K = 8
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A.3 Number of States Taken by Each Cycle in Instruction Execution
Execution Status
(Instruction Cycle)
Access Location
On-Chip Memory On-Chip Reg. Field
Instruction fetch
S_I
2
6
Branch address read S_J
Stack operation
S_K
Byte data access
S_L
3
Word data access
S_M
6
Internal operation
S_N
1
1
Notes: m: Number of wait states inserted in access to external device.
External Memory
6 + 2m
3+m
6 + 2m
1
615