HD64F3437TF16 Datasheet, PDF (495/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Flowchart for Erasing Multiple Blocks
Start
Set erase block registers
(set bits of block to be erased to 1)
Write 0 data to all addresses to be
erased (prewrite)*¹
n=1
Enable watchdog timer*²
Select erase mode (E bit = 1 in FLMCR)
Wait (x)ms*⁵
Clear E bit
Disable watchdog timer
Erasing
ends
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (t_vs1) µs*⁶
Notes: *1 Program all addresses to be erased
by following the prewrite flowchart.
*2 Set the watchdog timer overflow
interval to the value indicated in table
20.10.
*3 For the erase-verify dummy write,
write H'FF with a byte transfer
instruction.
*4 Read the data to be verified with a
byte transfer instruction. When
erasing two or more blocks, clear the
bits of erased blocks in the erase
block register, so that only unerased
blocks will be erased again.
*5 The erase time x is successively
incremented by the initial set value ×
2^n–1 (n = 1, 2, 3, 4). After fourth
erasing, the erase time is fixed. An
initial value of 6.25 ms or less should
be set, and the time for one erasure
should be 50 ms or less.
*6 t_VS1: 4 µs or more
t_VS2: 2 µs or more
N: 602 (Set N so that total
erase time does not exceed
30s.)
Erase-verify
next block
Set top address of block as
verify address
Dummy write to verify address*³
(flash memory latches address)
Wait (t_vs2) µs*⁶
Address + 1 → Address
No
Verify*⁴
(read data = H'FF?)
OK
Last address
in block?
Yes
No go
Clear EBR bit of erased block
Erase-verify next block
All erased blocks
No
verified?
Yes
466
No
All erased blocks
verified?
Yes
Clear EV bit
All blocks erased?
(EBR1 = EBR2 = 0?)
No
Yes
End of erase
n ≥ 4?
No
Double Erase time
(x × 2→x)
n ≥ N?*⁶
Yes
Erase error
Yes
No
n+1→n
Figure 20.11 Multiple-Block Erase Flowchart