HD64F3437TF16 Datasheet, PDF (68/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

2.5.5 Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8 Bit-Manipulation Instructions
Instruction
BSET
Size*
B
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
BOR
B
BIOR
BXOR
B
Note: * Size: Operand size
B: Byte
Function
1 → (<bit no.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
0 → (<bit no.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
¬ (<bit no.> of <EAd>) → (<bit no.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
¬ (<bit no.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit is specified by a bit number,
given in 3-bit immediate data or the lower three bits of a general
register.
C ∧ (<bit no.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory.
C ∧ [¬ (<bit no.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
C ∨ (<bit no.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory.
C ∨ [¬ (<bit no.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
C ⊕ (<bit no.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory.
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