HD64F3437TF16 Datasheet, PDF (362/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Slave CPU
Master CPU
Write to ODR
Write 1 to P4DR
P4DR = 0?
No
Yes
All bytes
No
transferred?
Yes
HIRQ output high
HIRQ output low
Interrupt initiation
ODR read
Hardware operations
Software operations
Figure 14.3 HIRQ Output Flowchart
14.5 Application Note
The host interface provides buffering of asynchronous data from the host and slave processors, but
an interface protocol must be followed to implement necessary functions and avoid data
contention. For example, if the host and slave processors try to access the same input or output
data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple
and effective protocol.
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