HD64F3437TF16 Datasheet, PDF (42/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Pin No.
Type
FP-100B,
Symbol TFP-100B I/O Name and Function
Bus control
WAIT
16
I
Wait: Requests the CPU to insert wait
states into the bus cycle when an external
address is accessed.
RD
22
O Read: Goes low to indicate that the CPU is
reading an external address.
WR
19
O Write: Goes low to indicate that the CPU is
writing to an external address.
AS
18
O Address strobe: Goes low to indicate that
there is a valid address on the address bus.
Interrupt signals NMI
7
I
Nonmaskable interrupt: Highest-priority
interrupt request. The NMIEG bit in the
system control register (SYSCR) determines
whether the interrupt is recognized at the
rising or falling edge of the NMI input.
IRQ₀ to 23 to 25,
I
IRQ₇
97 to 99,
34, 35
Interrupt request 0 to 7: Maskable interrupt
request pins.
Operating mode MD₁
5
control
MD₀
6
I
Mode: Input pins for setting the MCU mode
operating mode according to the table
below.
MD₁ MD₀ Mode Description
0
0
Mode 0 Illegal setting*
0
1
Mode 1 Expanded mode
with on-chip ROM
disabled
1
0
Mode 2 Expanded mode
with on-chip ROM
enabled
1
1
Mode 3 Single-chip mode
Note: * In the H8/3437SF (S-mask model,
single-power-supply on-chip flash
memory version), the settings MD₁ =
MD₀ = 0 are used when boot mode is
set. For details, see section 21.3,
On-Board Programming Modes.
Do not change the mode pin settings while
the chip is operating.
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