HD64F3437TF16 Datasheet, PDF (233/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

9.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable
bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 9.3
lists information about these interrupts.
Table 9.3 8-Bit Timer Interrupts
Interrupt
CMIA
CMIB
OVI
Description
Requested by CMFA
Requested by CMFB
Requested by OVF
Priority
High
Low
9.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle.
The control bits are set as follows:
1. In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when
its value matches the constant in TCORA.
2. In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match
A and to 0 on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
H'FF
TCORA
TCORB
H'00
TCNT
Clear counter
TMO pin
Figure 9.9 Example of Pulse Output
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