HD64F3437TF16 Datasheet, PDF (743/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Port Name
(Multiplexed
Pin Names) Mode
Reset
Hardware
Standby
Mode
Software
Standby Mode Sleep Mode
Program
Execution
State (Normal
Operation)
P8₆ to P8₀ 1
T
T
2
keep^*2
keep
I/O port
3
P9₇/WAIT 1
T
T
2
T/keep^*2
T/keep
WAIT/
I/O port
3
keep^*2
keep
I/O port
P9₆/ø
1
Clock T
H
2
output
Clock
output
Clock
output
3
T
(DDR = 1)
H
(DDR = 0)
T
(DDR = 1)
Clock output
(DDR = 0)
T
(DDR = 1)
Clock output
(DDR = 0)
Input port
P9₅ to P9₃, 1
H
T
H
AS, WR, RD 2
H
AS, WR, RD
3
T
keep
keep
I/O port
P9₂ to P9₀ 1
T
T
2
keep
keep
I/O port
3
PA₇ to PA₀ 1
T
T
2
keep^*2
keep
I/O port
3
PB₇ to PB₀ 1
T
T
2
keep^*2
keep
I/O port
3
Legend:
H: High level
L: Low level
T: High impedance
keep: Input port becomes high-impedance (when DDR = 0 and PCR = 1, MOS input pull-ups
remain on), output port retains state
Notes: *1 With address outputs, the last address accessed is retained.
*2 As on-chip supporting modules are initialized, becomes an I/O port determined by DDR
and DR.
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