HD64F3437TF16 Datasheet, PDF (107/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
Stack area
SP(R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR^*
PC (upper byte)
PC (lower byte)
Even address
Before interrupt
is accepted
Pushed onto stack
After interrupt
is accepted
PC: Program counter
CCR: Condition code register
SP: Stack pointer
Notes: 1. The PC contains the address of the first instruction executed after return.
2. Registers must be saved and restored by word access at an even address.
* Ignored on return.
Figure 4.6 Usage of Stack in Interrupt Handling
The CCR is comprised of one byte, but when it is saved to the stack, it is treated as one word of
data. During interrupt processing, two identical bytes of CCR data are saved to the stack to create
one word of data. When the RTE instruction is executed to restore the value from the stack, the
byte located at the even address is loaded into CCR, and the byte located at the odd address is
ignored.
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