HD64F3437TF16 Datasheet, PDF (347/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

14.1.1 Block Diagram
Figure 14.1 is a block diagram of the host interface.
CS₁
ECS₂/CS₂
IOR
EIOW/IOW
HA₀
HIRQ₁
HIRQ₁₁
HIRQ₁₂
GA₂₀
(Internal interrupt signals)
IBF2 IBF1
HDB₇–HDB₀/
XDB₇–XDB₀
Control
logic
Host
interrupt
request
Fast
A₂₀
gate
control
Port 4
Port 8
IDR1
ODR1
STR1
IDR2
ODR2
STR2
HICR
Internal data bus
Bus
interface
Legend:
IDR1: Input data register 1
IDR2: Input data register 2
ODR1: Output data register 1
ODR2: Output data register 2
STR1: Status register 1
STR2: Status register 2
HICR: Host interface control register
Figure 14.1 Host Interface Block Diagram
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