HD64F3437TF16 Datasheet, PDF (555/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Error Protection: In error protection, an error is detected when microcontroller runaway occurs
during flash memory programming/erasing, or operation is not performed in accordance with the
program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
If the microcontroller malfunctions during flash memory programming/erasing, the FLER bit is set
to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,
PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
1. When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
2. Immediately after the start of exception handling (excluding a reset) during
programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the bus is released during programming/erasing
Error protection is released only by a power-on reset.
Figure 21.14 shows the flash memory state transition diagram.
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