HD64F3437TF16 Datasheet, PDF (282/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Note: If possible, the error should be within 1%.
B=
F
64 × 2^2n–1 × (N + 1)
× 10⁶
F
N=
64 × 2^2n–1 × B
× 10⁶ – 1
B: Bit rate (bits/second)
N: Baud rate generator BRR value (0 ≤ N ≤ 255)
F: ø_P (MHz) when n ≠ 0, or ø (MHz) when n = 0
n: Baud rate generator input clock (n = 0, 1, 2, 3)
The meaning of n is given below.
SMR
WSCR
n
CKS1
CKS0
CKDBL Clock
0
0
0
0
ø
1
0
1
0
ø/4
2
1
0
0
ø/16
3
1
1
0
ø/64
0
0
0
1
ø
1
0
1
1
ø/8
2
1
0
1
ø/32
3
1
1
1
ø/128
The bit rate error can be calculated with the formula below.
F × 10⁶
Error (%) = _{(N + 1) × B × 64 × 22n–1} – 1 ^{× 100}
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