HD64F3437TF16 Datasheet, PDF (444/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

19.5 Flash Memory Emulation by RAM
Erasing and programming flash memory takes time, which can make it difficult to tune parameters
and other data in real time. If necessary, real-time updates of flash memory can be emulated by
overlapping the small-block flash-memory area with part of the RAM (H'FC00 to H'FD7F). This
RAM reassignment is performed using bits 7 and 6 of the wait-state control register (WSCR).
After a flash memory area has been overlapped by RAM, the RAM area can be accessed from two
address areas: the overlapped flash memory area, and the original RAM area (H'FC00 to H'FD7F).
Table 19.11 indicates how to reassign RAM.
Wait-State Control Register (WSCR)^*2
Bit
7
6
5
4
3
2
1
RAMS RAM0 CKDBL
—
WMS1 WMS0 WC1
Initial value^*1
0
0
0
0
1
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
WC0
0
R/W
Notes: *1 WSCR is initialized by a reset and in hardware standby mode. It is not initialized in
software standby mode.
*2 For details of WSCR settings, see section 19.2.4, Wait-State Control Register (WSCR).
Table 19.11 RAM Area Selection
Bit 7: RAMS
0
1
Bit 6: RAMO
0
1
0
1
RAM Area
None
H'FC80 to H'FCFF
H'FC80 to H'FD7F
H'FC00 to H'FC7F
ROM Area
—
H'0080 to H'00FF
H'0080 to H'017F
H'0000 to H'007F
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