HD64F3437TF16 Datasheet, PDF (686/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

SYSCR—System Control Register
H'C4
System Control
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME
0
0
0
0
1
0
0
1
R/W
R/W R/W
R/W
R
R/W
R/W
R/W
RAM Enable
0 On-chip RAM is disabled.
1 On-chip RAM is enabled. (initial value)
Host Interface Enable
0 Host interface is prohibited (initial value)
1 Host interface is allowed (slave mode)
NMI Edge
0 Falling edge of NMI is detected.
1 Rising edge of NMI is detected.
External Reset
0 Reset was caused by watchdog timer overflow
1 Reset was caused by external reset signal (initial value)
Standby Timer Select 2 to 0 (ZTAT and Mask ROM Versions)
0 0 0 Clock settling time = 8,192 states (initial value)
0 0 1 Clock settling time = 16,384 states
0 1 0 Clock settling time = 32,768 states
0 1 1 Clock settling time = 65,536 states
1 0 — Clock settling time = 131,072 states
1 1 — Unused
Standby Timer Select 2 to 0 (F-ZTAT Version)
0 0 0 Settling time = 8,192 states (initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 0 Settling time = 131,072 states
1 0 1 Settling time = 1,024 states
1 1 — Unused
Software Standby
0 SLEEP instruction causes transition to sleep mode. (initial value)
1 SLEEP instruction causes transition to software standby mode.
657