HD64F3437TF16 Datasheet, PDF (478/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Boot-Mode Execution Procedure: Figure 20.4 shows the boot-mode execution procedure.
Start
1
Program H8/3437F pins for boot mode,
and reset
2
Host transmits H'00 data continuously
at desired bit rate
H8/3437F measures low period
of H'00 data transmitted from host
3
H8/3437F computes bit rate and
sets bit rate register
After completing bit-rate alignment, H8/3437F
4
sends one H'00 data byte to host to indicate
that alignment is completed
Host checks that this byte, indicating
5
completion of bit-rate alignment, is received
normally, then transmits one H'55 byte
6
After receiving H'55, H8/3437F sends part of
the boot program to RAM
H8/3437F branches to the RAM boot
area (H'F800 to H'FF2F), then checks the
data in the user area of flash memory
7
All data = H'FF?^*4
No
Yes
Erase all flash
memory blocks^{*3, *4}
After checking that all data in flash memory is H'FF,
H8/3437F transmits one H'AA data byte to host
8
H8/3437F receives two bytes indicating byte
length (N) of program to be downloaded
to on-chip RAM^*1
H8/3437F transfers one user program
byte to RAM^*2
H8/3437F calculates number of bytes left
9
to be transferred (N = N – 1)
All bytes transferred?
No
(N = 0?)
Yes
After transferring the user program to RAM,
H8/3437F transmits one H'AA data byte to host
10
H8/3437F branches to H'F7E0 in RAM area and
executes user program downloaded into RAM
1. Program the H8/3437F pins for boot mode, and start the
H8/3437F from a reset.
2. Set the host’s data format to 8 bits + 1 stop bit, select the
desired bit rate (2400, 4800, or 9600 bps), and transmit
H'00 data continuously.
3. The H8/3437F repeatedly measures the low period of the
RxD1 pin and calculates the host’s asynchronous-
communication bit rate.
4. When SCI bit-rate alignment is completed, the H8/3437F
transmits one H'00 data byte to indicate completion of
alignment.
5. The host should receive the byte transmitted from the
H8/3437F to indicate that bit-rate alignment is completed,
check that this byte is received normally, then transmit one
H'55 byte.
6. After receiving H'55, H8/3437F sends part of the boot
program to H'F780 to H'F7DF and H'F800 to H'FF2F of
RAM.
7. After branching to the boot program area (H'F800 to
H'FF2F) in RAM, the H8/3437F checks whether the flash
memory already contains any programmed data. If so, all
blocks are erased.
8. After the H8/3437F transmits one H'AA data byte, the host
transmits the byte length of the user program to be
transferred to the H8/3437F. The byte length must be sent
as two-byte data, upper byte first and lower byte second.
After that, the host proceeds to transmit the user program.
As verification, the H8/3437F echoes each byte of the
received byte-length data and user program back to the
host.
9. The H8/3437F stores the received user program in on-chip
RAM in a 1934-byte area from H'F7E0 to H'FF6D.
10. After transmitting one H'AA data byte, the H8/3437F
branches to address H'F7E0 in on-chip RAM and executes
the user program stored in the area from H'F7E0 to
H'FF6D.
Notes: *1 The user can use 1934 bytes of RAM. The number
of bytes transferred must not exceed 1934 bytes.
Be sure to transmit the byte length in two bytes,
upper byte first and lower byte second. For
example, if the byte length of the program to be
transferred is 256 bytes (H'0100), transmit H'01 as
the upper byte, followed by H'00 as the lower byte.
*2 The part of the user program that controls the flash
memory should be coded according to the flash
memory write/erase algorithms given later.
*3 If a memory cell malfunctions and cannot be
erased, the H8/3437F transmits one H'FF byte to
report an erase error, halts erasing, and halts
further operations.
*4 H'0000 to H'EF7F in mode 2 and H'0000 to H'F77F
in mode 3.
Figure 20.4 Boot Mode Flowchart
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