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HD64F3437TF16 Datasheet, PDF (428/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device. | |||
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19.4.6 Erasing Flowchart and Sample Program
Flowchart for Erasing One Block
Start
Set erase block register
(set bit of block to be erased to 1)
Write 0 data in all addresses
to be erased (prewrite)*1
n=1
Enable watchdog timer*2
Select erase mode
(E bit = 1 in FLMCR)
Wait (x) ms*5
Clear E bit
Disable watchdog timer
Set top address in block
as verify address
Select erase-verify mode
(EV bit = 1 in FLMCR)
Wait (tVS1) µs*5
Notes: *1 Program all addresses to be
erased by following the prewrite
flowchart.
*2 Set the watchdog timer overflow
interval to the value indicated in
table 19.10.
Erasing ends
*3 For the erase-verify dummy write,
write H'FF with a byte transfer
instruction.
*4 Read the data to be verified with
a byte transfer instruction. When
erasing two or more blocks, clear
the bits of erased blocks in the
erase block registers, so that only
unerased blocks will be erased
again.
*5 x: 10 ms
tVS1: 4 µs or more
tVS2: 2 µs or more
N: 3000
Dummy write to verify address*3
(flash memory latches address)
Wait (tVS2) µs*5
Verify*4 (read data H'FF?)
No
Address + 1 â address
OK
Last address?
Yes
Clear EV bit
Clear erase block register
(clear bit of erased block to 0)
No go
End of block erase
Clear EV bit
n ⥠N?*5
Yes
Erase error
Figure 19.9 Erasing Flowchart
Erase-verify ends
No
n+1ân
399
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