HD64F3437TF16 Datasheet, PDF (214/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Contention between OCR Write and Compare-Match: If a compare-match occurs during the
T₃ state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
compare-match signal is inhibited.
Figure 8.18 shows this type of contention.
Write cycle:
CPU write to lower byte of OCRA or OCRB
T₁
T₂
T₃
ø
Internal address bus
OCR address
Internal write signal
FRC
N
N+1
OCRA or OCRB
N
M
Write data
Compare-match
A or B signal
Inhibited
Figure 8.18 Contention between OCR Write and Compare-Match
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