HD64F3437TF16 Datasheet, PDF (257/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

11.3.2 Interval Timer Mode
Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1.
In interval timer mode, an WOVF request is generated each time the timer count overflows. This
function can be used to generate WOVF requests at regular intervals. See figure 11.4.
H'FF
TCNT count
H'00
Time t
WT/IT = 0 OVF
OVF
OVF
OVF
OVF
TME = 1 request request request request request
Figure 11.4 Operation in Interval Timer Mode
11.3.3 Setting the Overflow Flag
The WOVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module
requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 11.5.
ø
TCNT
Internal overflow
signal
H'FF H'00
OVF
Figure 11.5 Setting the OVF Bit
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