HD64F3437TF16 Datasheet, PDF (191/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

8.2.4 Timer Interrupt Enable Register (TIER)
Bit
7
6
5
4
3
2
1
0
ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE
—
Initial value
0
0
0
0
0
0
0
1
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in the standby modes.
Bit 7—Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to 1.
Bit 7: ICIAE
0
1
Description
Input capture interrupt request A (ICIA) is disabled.
Input capture interrupt request A (ICIA) is enabled.
(Initial value)
Bit 6—Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6: ICIBE
0
1
Description
Input capture interrupt request B (ICIB) is disabled.
Input capture interrupt request B (ICIB) is enabled.
(Initial value)
Bit 5—Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5: ICICE
0
1
Description
Input capture interrupt request C (ICIC) is disabled.
Input capture interrupt request C (ICIC) is enabled.
(Initial value)
Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4: ICIDE
0
1
Description
Input capture interrupt request D (ICID) is disabled.
Input capture interrupt request D (ICID) is enabled.
(Initial value)
162