HD64F3437TF16 Datasheet, PDF (58/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 2.2 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register direct, Rn
Effective Address
Calculation
15
87 43 0
op regm regn
2
Register indirect, @Rn
15
op
76 43 0
reg
15
0
16-bit register contents
3
Register indirect with
displacement, @(d:16, Rn) ¹⁵
0
16-bit register contents
15
op
76 43 0
reg
disp
disp
4
Register indirect with
post-increment, @Rn+
15
0
16-bit register contents
15
op
76 43 0
reg
Register indirect with
pre-decrement, @–Rn
1 or 2*
15
0
16-bit register contents
15
op
76 43 0
reg
1 or 2*
Note: * 1 for a byte operand,
2 for a word operand
Effective Address
3
03
0
regm regn
Operands are contained in
registers regm and regn
15
0
15
0
15
0
15
0
29