HD64F3437TF16 Datasheet, PDF (597/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 23.8 Bus Timing
Condition A: V_CC = 5.0 V ±10%, V_CCB = 5.0 V ±10%, V_SS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20 to +75˚C (regular specifications), Ta = –40 to +85˚C
(wide-range specifications)
Condition B: V_CC = 4.0 V to 5.5 V, V_CCB = 4.0 V to 5.5 V, V_SS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20 to +75˚C (regular specifications), Ta = –40 to +85˚C
(wide-range specifications)
Condition C: V_CC = 2.7 V to 5.5 V^*3, V_CCB = 2.7 V to 5.5 V^*3, V_SS = 0 V, ø = 2.0 MHz to
maximum operating frequency, Ta = –20 to +75˚C
Condition C Condition B Condition A
Item
10 MHz
Symbol Min Max
12 MHz
Min Max
16 MHz
Min Max
Test
Unit Conditions
Clock cycle time
t_cyc
100 500
83.3 500
62.5 500 ns
Clock pulse width low
t_CL
30 —
30 —
20 —
ns
Clock pulse width high
t_CH
30 —
30 —
20 —
ns
Clock rise time
t_Cr
— 20
— 10
— 10
ns
Clock fall time
t_Cf
— 20
— 10
— 10
ns
Address delay time
t_AD
— 50
— 35
— 30
ns
Address hold time
t_AH
20 —
15 —
10 —
ns
Address strobe delay time t_ASD
— 50
— 35
— 30
ns
Write strobe delay time t_WSD
— 50
— 35
— 30
ns
Strobe delay time
t_SD
— 50
— 35
— 30
ns
Write strobe pulse width^*1 t_WSW
110 —
90 —
60 —
ns
Address setup time 1^*1
t_AS1
15 —
10 —
10 —
ns
Address setup time 2^*1
t_AS2
65 —
50 —
40 —
ns
Read data setup time
t_RDS
35 —
20 —
20 —
ns
Read data hold time^*1
t_RDH
0
—
0
—
0
—
ns
Read data access time^*1 t_ACC
— 170
— 160
— 110 ns
Write data delay time
t_WDD
—
80/75^*2 —
65/60^*2 —
60
ns
Write data setup time
t_WDS
0/5^*2 —
0/5^*2 —
0/5^*2 —
ns
Write data hold time
t_WDH
20 —
20 —
20 —
ns
Wait setup time
t_WTS
40 —
35 —
30 —
ns
Wait hold time
t_WTH
10 —
10 —
10 —
ns
Notes: *1 Values at maximum operating frequency
*2 H8/3437 F-ZTAT version/other products
*3 In the F-ZTAT LH version, V_CC = 3.0 V to 5.5 V, V_CCB = 3.0 V to 5.5 V
Fig. 23.7
Fig. 23.8
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