HD64F3437TF16 Datasheet, PDF (176/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Port A Data Direction Register (PADDR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
PA₇DDR PA₆DDR PA₅DDR PA₄DDR PA₃DDR PA₂DDR PA₁DDR PA₀DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin
functions as an output pin if the corresponding PADDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a PADDR bit
is set to 1, the corresponding pin remains in the output state.
Port A Output Data Register (PAODR)
Bit
7
PA₇
Initial value
0
Read/Write R/W
6
PA₆
0
R/W
5
PA₅
0
R/W
4
PA₄
0
R/W
3
PA₃
0
R/W
2
PA₂
0
R/W
1
PA₁
0
R/W
0
PA₀
0
R/W
PAODR is an 8-bit register that stores data for pins PA₇ to PA₀. PAODR can always be written to
and read, regardless of the PADDR settings.
PAODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port A Input Data Register (PAPIN)
Bit
7
6
5
4
3
2
1
0
PA₇
PA₆
PA₅
PA₄
PA₃
PA₂
PA₁
PA₀
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note: * Depends on the levels of pins PA₇ to PA₀.
When PAPIN is read, the pin states are always read.
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