HD64F3437TF16 Datasheet, PDF (254/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 4—Reserved: This bit cannot be modified and is always read as 1.
Bit 3: Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at
watchdog timer overflow.
Bit 3: RST/NMI
0
1
Description
NMI function enabled
Reset function enabled
(Initial value)
Bits 2–0—Clock Select (CKS2–CKS0): These bits select one of eight clock sources obtained by
dividing the system clock (ø).
The overflow interval is the time from when the watchdog timer counter begins counting from
H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this
interval.
Bit 2:
CKS2
0
1
Bit 1:
CKS1
0
1
0
1
Bit 0:
CKS0
0
1
0
1
0
1
0
1
Clock Source
ø_P/2
ø_P/32
ø_P/64
ø_P/128
ø_P/256
ø_P/512
ø_P/2048
ø_P/4096
Overflow Interval (ø_P = 10 MHz)
51.2 µs
(Initial value)
819.2 µs
1.6 ms
3.3 ms
6.6 ms
13.1 ms
52.4 ms
104.9 ms
225