HD64F3437TF16 Datasheet, PDF(270/752 Page) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD64F3437TF16 Datasheet, PDF (270/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

◁

Bit 6âReceive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt

(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is

set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing

error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1.

Bit 6: RIE

0

1

Description

The receive-end interrupt (RXI) and receive-error (ERI) requests are disabled.

(Initial value)

The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.

Bit 5âTransmit Enable (TE): This bit enables or disables the transmit function. When the

transmit function is enabled, the TxD pin is automatically used for output. When the transmit

function is disabled, the TxD pin can be used as a general-purpose I/O port.

Bit 5: TE

0

1

Description

The transmit function is disabled.

(Initial value)

The TxD pin can be used for general-purpose I/O.

The transmit function is enabled. The TxD pin is used for output.

Bit 4âReceive Enable (RE): This bit enables or disables the receive function. When the receive

function is enabled, the RxD pin is automatically used for input. When the receive function is

disabled, the RxD pin is available as a general-purpose I/O port.

Bit 4: RE

0

1

Description

The receive function is disabled. The RxD pin can be used for general-purpose

I/O.

(Initial value)

The receive function is enabled. The RxD pin is used for input.

Bit 3âMultiprocessor Interrupt Enable (MPIE): When serial data is received in a

multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-

error interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or

disables the transfer of received data from RSR to RDR, and enables or disables setting of the

RDRF, FER, PER, and ORER bits in the serial status register (SSR).

The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode.

Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition

data is received regardless of the value of the multiprocessor bit in the receive data.

241

▷