HD64F3437TF16 Datasheet, PDF (258/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

11.3.4 RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI
bit is 1 at this time, an internal reset signal is generated for the entire chip. At the same time a low-
level signal is output from the RESO pin. The timing is shown in figure 11.6.
ø
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
H'FF
H'00
132 states
518 states
Figure 11.6 RESO Signal Output Timing
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