HD64F3437TF16 Datasheet, PDF (171/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Port 9
Pin configuration in master mode,
or when STAC bit is 0
P9₁/IRQ₁/EIOW
P9₀/IRQ₂/ADTRG/ECS₂
P9₁ (input/output)/IRQ₁ (input)
P9₀ (input/output)/IRQ₂ (input)/ADTRG (input)
Pin configuration in slave mode
when STAC bit is 1
IRQ₁ (input)/EIOW (input)
IRQ₂ (input)/ECS₂ (input)
Figure 7.17 Port 9 Pin Configuration (cont)
7.10.2 Register Configuration and Descriptions
Table 7.18 summarizes the port 9 registers.
Table 7.18 Port 9 Registers
Name
Abbreviation Read/Write
Port 9 data direction register P9DDR
W
Port 9 data register
P9DR
R/W^*1
Notes: *1 Bit 6 is read-only.
*2 Bit 6 is undetermined. Other bits are initially 0.
Initial Value
Address
H'40 (modes 1 and 2) H'FFC0
H'00 (mode 3)
Undetermined^*2
H'FFC1
142