HD64F3437TF16 Datasheet, PDF(556/752 Page) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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HD64F3437TF16 Datasheet, PDF (556/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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Program mode

Erase mode

RD VF PR ER FLER = 0

RES = 0 or STBY = 0

Error occurrence

Error occurrence

(software standby

mode)

RES = 0 or

STBY = 0

Reset or

hardware standby

(hardware protection)

RD VF PR ER FLER = 0

RES = 0 or

STBY = 0

FLMCR1, FLMCR2,

EBR2 initialized

Error protect mode

RD VF PR ER FLER = 1

Software standby mode

Software standby mode

release

Error protect mode

(standby)

RD VF PR ER FLER = 1

FLMCR1, FLMCR2 (except FLER bit),

EBR2 initialized

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

Figure 21.14 Flash Memory State Transitions

21.4.6 Interrupt Handling during Flash Memory Programming and Erasing

All interrupts, including NMI input, should be disabled when flash memory is being programmed

or erased (while the P or E bit is set in FLMCR1) and while the boot program is executing in boot

mode*1, to give priority to the program or erase operation. There are three reasons for this:

1. Interrupt occurrence during programming or erasing might cause a violation of the

programming or erasing algorithm, with the result that normal operation could not be assured.

2. In the interrupt exception handling sequence during programming or erasing, the vector would

not be read correctly*2, possibly resulting in microcontroller runaway.

3. If an interrupt occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

For these reasons, there are conditions for disabling interrupts in the on-board programming

modes alone, as an exception to the general rule. However, this provision does not guarantee

normal erasing and programming or microcontroller operation.

All requests, including NMI, must therefore be disabled inside and outside the microcontroller

when flash memory is programmed or erased. Interrupts are also disabled in the error protection

state while the P or E bit setting in FLMCR1 is held.

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