HD64F3437TF16 Datasheet, PDF (600/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 23.10 Timing Conditions of On-Chip Supporting Modules
Condition A: V_CC = 5.0 V ±10%, V_CCB = 5.0 V ±10%, V_SS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition B: V_CC = 4.0 V to 5.5 V, V_CCB = 4.0 V to 5.5V, V_SS = 0 V, ø = 2.0 MHz to maximum
operating frequency, Ta = –20˚C to +75˚C (regular specifications), Ta = –40˚C to
+85˚C (wide-range specifications)
Condition C: V_CC = 2.7 V to 5.5 V*, V_CCB = 2.7 V to 5.5 V*, V_SS = 0 V, ø = 2.0 MHz to
maximum operating frequency, Ta = –20˚C to +75˚C
Item
Symbol
FRT Timer output delay t_FTOD
time
Timer input setup t_FTIS
time
Timer clock input
setup time
t_FTCS
TMR
Timer clock pulse
width
Timer output delay
time
t_FTCWH
t_FTCWL
t_TMOD
Timer reset input
setup time
t_TMRS
Timer clock input
setup time
t_TMCS
Timer clock pulse t_TMCWH
width (single edge)
Timer clock pulse t_TMCWL
width (both edges)
PWM Timer output delay t_PWOD
time
SCI Input clock (Async) t_Scyc
cycle
(Sync)
Transmit data delay t_TXD
time (Sync)
Receive data setup t_RXS
time (Sync)
Receive data hold t_RXH
time (Sync)
Input clock pulse
width
t_SCKW
Condition C
10 MHz
Min Max
— 150
80 —
80 —
1.5 —
— 150
80 —
80 —
1.5 —
2.5 —
— 150
4
—
6
—
— 200
150 —
150 —
0.4 0.6
Condition B
12 MHz
Min Max
— 100
50 —
50 —
1.5 —
— 100
50 —
50 —
1.5 —
2.5 —
— 100
4
—
6
—
— 100
100 —
100 —
0.4 0.6
Condition A
16 MHz
Min Max Unit
— 100 ns
Test
Conditions
Fig. 23.13
50 — ns
50 — ns Fig. 23.14
1.5 —
t_cyc
— 100 ns Fig. 23.15
50 — ns Fig. 23.17
50 — ns Fig. 23.16
1.5 —
t_cyc
2.5 —
t_cyc
— 100 ns Fig. 23.18
4
—
t_cyc Fig. 23.19
6
—
t_cyc
— 100 ns
100 — ns
100 — ns
0.4 0.6 t_Scyc Fig. 23.20
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