HD64F3437TF16 Datasheet, PDF (356/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

14.2.9 Serial/Timer Control Register (STCR)
Bit
7
6
5
4
IICS
IICD IICX
IICE
Initial value
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
3
STAC
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
0
ICKS0
0
R/W
STCR is an 8-bit readable/writable register that controls the I²C bus interface and host interface,
controls the SCI operating mode, and selects the TCNT clock source in the 8-bit timers. STCR is
initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—I²C Control (IICS, IICD, IICX, IICE): These bits are used to control the I²C bus
interface. For details, see section 13, I²C Bus Interface.
Bit 3—Slave Input Switch (STAC): Controls switching of host interface input pins. Settings of
this bit are valid only when the host interface is enabled (slave mode).
Bit 3: STAC
0
1
Description
In port 8, P8₅ switches over to CS₂, and P8₄ to IOW
In port 9, P9₁ switches over to EIOW, and P9₀ to ECS₂
(Initial value)
Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of SCI0 and SCI1. For
details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): Together with bits CKS2
to CKS0 in TCR, these bits select timer counter clock inputs. For details, see section 9, 8-Bit
Timers.
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