HD64F3437TF16 Datasheet, PDF (346/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Section 14 Host Interface
14.1 Overview
The H8/3437 Series has an on-chip host interface (HIF) that provides a dual-channel parallel
interface between the on-chip CPU and a host processor. The host interface is available only when
the HIE bit is set to 1 in SYSCR. This mode is called slave mode, because it is designed for a
master-slave communication system in which the H8/3437-Series chip is slaved to a host
processor.
The host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte
control register, fast A₂₀ gate logic, and a host interrupt request circuit. Communication is carried
out via five control signals from the host processor (CS₁, CS₂ or ECS₂, HA₀, IOR, andIOW or
EIOW), four output signals to the host processor (GA₂₀, HIRQ₁, HIRQ₁₁, and HIRQ₁₂), and an 8-
bit bidirectional command/data bus (HDB₇ to HDB₀, or XDB₇ to XDB₀). The CS₁ and CS₂ (or
ECS₂) signals select one of the two interface channels.
Note: If one of the two interface channels will not be used, tie the unused CS pin to V_CC. For
example, if interface channel 1 (IDR1, ODR1, STR1) is not used, tie CS₁ to V_CC.
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