HD64F3437TF16 Datasheet, PDF(358/752 Page) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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HD64F3437TF16 Datasheet, PDF (358/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

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14.3.3 A20 Gate

The A20 gate signal can mask address A20 to emulate an addressing mode used by personal

computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be

output under software control, or a fast A20 gate signal can be output under hardware control. Fast

A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0).

Note: * Intel microprocessor.

Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1

command followed by data. When the slave processor receives data, it normally uses an interrupt

routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command,

software copies bit 1 of the data and outputs it at the gate A20 pin (P81/GA20).

Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast

A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. The initial output from

this pin will be a logic 1, which is the initial DR value. Afterward, the host processor can

manipulate the output from this pin by sending commands and data. This function is available

only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the

host processor. When an H'D1 host command is detected, bit 1 of the data following the host

command is output from the GA20 output pin. This operation does not depend on software or

interrupts, and is faster than the regular processing using interrupts. Table 14.6 lists the conditions

that set and clear GA20 (P81). Figure 14.2 describes the GA20 output in flowchart form. Table 14.7

indicates the GA20 output signal values.

Table 14.6 GA20 (P81) Set/Clear Timing

Pin Name

GA20 (P81)

Setting Condition

Rising edge of the hostâs write signal

(IOW) when bit 1 of the written data

is 1 and the data follows an H'D1

host command

Clearing Condition

Rising edge of the hostâs write signal

(IOW) when bit 1 of the written data is 0

and the data follows an H'D1 host

command

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