HD64F3437TF16 Datasheet, PDF (328/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

5. Software clears IRIC to 0 in ICSR.
6. To continue transmitting, write the next transmit data in ICDR. Transmission of the next byte
will begin in synchronization with the internal clock.
Steps 4 to 6 can be repeated to transmit data continuously. To end the transmission, write 0 in
BBSY and 0 in SCP in ICSR. This generates a stop condition by causing a low-to-high transition
of SDA while SCL is high.
SCL
SDA (master
output)
1 234 5 67 89
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
Bit 7
SDA (slave
output)
IRIC
A
Interrupt
request
User
processing
2. Write BBSY = 1
and SCP = 0
3. Write to ICDR
5. Clear IRIC 6. Write to ICDR
Figure 13.6 Timing in Master Transmit Mode
(MLS = WAIT = ACK = 0)
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