HD64F3437TF16 Datasheet, PDF (224/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and
ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for
the timer counter. Six internal clock sources, derived by prescaling the system clock, are available
for each timer channel. For internal clock sources the counter is incremented on the falling edge of
the internal clock. For an external clock source, these bits can select whether to increment the
counter on the rising or falling edge of the clock input (TMCI), or on both edges.
TCR
Bit 2: Bit 1: Bit 0:
Channel CKS2 CKS1 CKS0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
STCR
Bit 1: Bit 0:
ICKS1 ICKS0 Description
—
—
No clock source (timer stopped) (Initial value)
0
ø_P/8 internal clock, counted on falling edge
1
ø_P/2 internal clock, counted on falling edge
0
ø_P/64 internal clock, counted on falling edge
1
ø_P/32 internal clock, counted on falling edge
0
ø_P/1024 internal clock, counted on falling edge
1
ø_P/256 internal clock, counted on falling edge
—
No clock source (timer stopped)
External clock source, counted on rising edge
External clock source, counted on falling edge
External clock source, counted on both rising
and falling edges
—
—
No clock source (timer stopped) (Initial value)
0
ø_P/8 internal clock, counted on falling edge
1
ø_P/2 internal clock, counted on falling edge
0
ø_P/64 internal clock, counted on falling edge
1
ø_P/128 internal clock, counted on falling edge
0
ø_P/1024 internal clock, counted on falling edge
1
ø_P/2048 internal clock, counted on falling edge
—
No clock source (timer stopped)
External clock source, counted on rising edge
External clock source, counted on falling edge
External clock source, counted on both rising
and falling edges
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