HD64F3437TF16 Datasheet, PDF (355/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR2.
Bit 1: IBF
0
1
Description
This bit is cleared when the slave processor reads IDR2
This bit is set when the host processor writes to IDR2
(Initial value)
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to
0 when the host processor reads ODR2.
Bit 0: OBF
0
1
Description
This bit is cleared when the host processor reads ODR2
This bit is set when the slave processor writes to ODR2
(Initial value)
Table 14.4 shows the conditions for setting and clearing the STR2 flags.
Table 14.4 Set/Clear Timing for STR2 Flags
Flag
C/D
IBF
OBF
Setting Condition
Rising edge of host’s write signal (IOW)
when HA₀ is high
Rising edge of host’s write signal (IOW)
when writing to IDR2
Falling edge of slave’s internal write
signal (WR) when writing to ODR2
Clearing Condition
Rising edge of host’s write signal (IOW)
when HA₀ is low
Falling edge of slave’s internal read signal
(RD) when reading IDR2
Rising edge of host’s read signal (IOR)
when reading ODR2
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