HD64F3437TF16 Datasheet, PDF (100/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bits 7 to 0—IRQ₇ to IRQ₀ Sense Control (IRQ7SC to IRQ0SC): These bits determine whether
IRQ₇ to IRQ₀ are level-sensed or sensed on the falling edge.
Bits 7 to 0:
IRQ7SC to IRQ0SC
0
1
Description
An interrupt is generated when IRQ₇ to IRQ₀ inputs are low. (Initial state)
An interrupt is generated by the falling edge of the IRQ₇ to IRQ₀ inputs.
IRQ Enable Register (IER)
Bit
Initial value
R/W
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ₇ to
IRQ₀ interrupts individually.
Bits 7 to 0:
IRQ7E to IRQ0E
0
1
Description
IRQ₇ to IRQ₀ interrupt requests are disabled.
IRQ₇ to IRQ₀ interrupt requests are enabled.
(Initial state)
When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to
IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit
(IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is
cleared to 0 while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the
interrupt-handling routine can be executed even though the enable bit is now 0.
If execution of interrupt-handling routines under these conditions is not desired, it can be avoided
by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
when execution jumps to an interrupt vector.
2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests.
3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn
interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.
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