HD64F3437TF16 Datasheet, PDF (641/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Mnemonic
Operation
Addressing Mode/
Instruction Length
Condition Code
JSR @@aa:8
RTS
RTE
SLEEP
— SP–2 → SP
PC → @SP
PC ← @aa:8
— PC ← @SP
SP+2 → SP
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
— Transit to sleep mode.
I HNZVC
2 —————— 8
2 —————— 8
2
10
2 —————— 2
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
B #xx:8 → CCR
B Rs8 → CCR
B CCR → Rd8
B CCR∧#xx:8 → CCR
B CCR∨#xx:8 → CCR
B CCR⊕#xx:8 → CCR
— PC ← PC+2
2
2
2
2
2
2
2
2
—————— 2
2
2
2
2 —————— 2
Notes: The number of states is the number of states required for execution when the instruction
and its operands are located in on-chip memory.
(1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0.
(4) The number of states required for execution is 4n+8 (n = value of R4L).
(5) These instructions are not supported by the H8/3437 Series.
(6) Set to 1 if the divisor is negative; otherwise cleared to 0.
(7) Set to 1 if the divisor is 0; otherwise cleared to 0.
612