HD64F3437TF16 Datasheet, PDF (109/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

4.3.6 Interrupt Response Time
Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since on-chip memory is
accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling
routines in on-chip ROM and the stack in on-chip RAM.
Table 4.4 Number of States before Interrupt Service
Number of States
No.
Reason for Wait
On-Chip Memory
External Memory
1
Interrupt priority decision
2^{* 3}
2^{* 3}
2
Wait for completion of current 1 to 13
instruction^*1
5 to 17^*2
3
Save PC and CCR
4
12^*2
4
Fetch vector
2
6^{* 2}
5
Fetch instruction
4
12^*2
6
Internal processing
4
4
Total
17 to 29
41 to 53^*2
Notes: *1 These values do not apply if the current instruction is EEPMOV.
*2 If wait states are inserted in external memory access, add the number of wait states.
*3 1 for internal interrupts.
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