HD64F3437TF16 Datasheet, PDF (541/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Table 21.5 Flash Memory Erase Blocks
Block (Size)
60-Kbyte Version
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (12 kbytes)
EB7 (2 kbytes)
Addresses
H'0000–H'03FF
H'0400–H'07FF
H'0800–H'0BFF
H'0C00–H'0FFF
H'1000–H'7FFF
H'8000–H'BFFF
H'C000–H'EF7F
H'EF80–H'F77F
21.2.4 Wait-State Control Register (WSCR)
Bit
7
—
Initial value
0
Read/Write R/W
6
5
4
3
2
— CKDBL FLSHE WMS1 WMS0
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
1
WC1
0
R/W
0
WC0
0
R/W
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals
supplied to the supporting modules. It also controls wait state controller wait settings, RAM area
setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply
flash memory control registers.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Reserved: These bits are reserved, but can be written and read. Their initial value
is 0.
Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to the on-
chip supporting modules. For details, see section 6, Clock Pulse Generator.
512