HD64F3437TF16 Datasheet, PDF (269/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bit 2—Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous
communication. When multiprocessor format is selected, the parity settings of the parity enable bit
(PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication.
The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to 1.
When the MPE bit is cleared to 0, the multiprocessor communication function is disabled
regardless of the setting of the MP bit.
Bit 2: MP
0
1
Description
Multiprocessor communication function is disabled.
Multiprocessor communication function is enabled.
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the
on-chip baud rate generator.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
ø clock
ø_P/4 clock
ø_P/16 clock
ø_P/64 clock
(Initial value)
12.2.6 Serial Control Register (SCR)
Bit
7
6
5
TIE
RIE
TE
Initial value
0
0
0
Read/Write R/W
R/W
R/W
4
3
2
1
0
RE
MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
SCR is an 8-bit readable/writable register that enables or disables various SCI functions.
It is initialized to H'00 by a reset and in the standby modes.
Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt
(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register
(SSR) is set to 1.
Bit 7: TIE
0
1
Description
The TDR-empty interrupt request (TXI) is disabled.
The TDR-empty interrupt request (TXI) is enabled.
(Initial value)
240