HD64F3437TF16 Datasheet, PDF (350/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

14.2 Register Descriptions
14.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
XRST NMIEG HIE
1
0
0
R
R/W
R/W
0
RAME
1
R/W
SYSCR is an 8-bit read/write register which controls chip operations. Host interface functions are
enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for
information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset and in
hardware standby mode.
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the
host interface handles host-slave data transfers, operating in slave mode.
Bit 1: HIE
0
1
Description
The host interface is disabled
The host interface is enabled (slave mode)
(Initial value)
14.2.2 Host Interface Control Register (HICR)
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
Slave Read/Write —
—
—
—
Host Read/Write —
—
—
—
3
2
1
0
— IBFIE2 IBFIE1 FGA20E
1
0
0
0
—
R/W
R/W
R/W
—
—
—
—
HICR is an 8-bit read/write register which controls host interface interrupts and the fast A₂₀ gate
function. HICR is initialized to H'F8 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
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