HD64F3437TF16 Datasheet, PDF (316/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

13.2 Register Descriptions
13.2.1 I²C Bus Data Register (ICDR)
Bit
Initial value
Read/Write
7
ICDR7
—
R/W
6
ICDR6
—
R/W
5
ICDR5
—
R/W
4
ICDR4
—
R/W
3
ICDR3
—
R/W
2
ICDR2
—
R/W
1
ICDR1
—
R/W
0
ICDR0
—
R/W
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. Transmitting is started by writing data in
ICDR. Receiving is started by reading data from ICDR.
ICDR is also used as a shift register, so it must not be written or read until data has been
completely transmitted or received. Read or write access while data is being transmitted or
received may result in incorrect data.
The ICDR value following a reset and in hardware standby mode is undetermined.
13.2.2 Slave Address Register (SAR)
Bit
7
6
5
4
3
2
1
0
SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0
FS
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first byte received after a start condition, the
chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
differing from the addresses of other slave devices connected to the I²C bus.
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