HD64F3437TF16 Datasheet, PDF (225/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

9.2.4 Timer Control/Status Register (TCSR)
Bit
7
6
5
4
CMFB CMFA OVF
—
Initial value
0
0
0
1
Read/Write R/(W)* R/(W)* R/(W)* —
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
TCSR is initialized to H'10 by a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7: CMFB
0
1
Description
To clear CMFB, the CPU must read CMFB after it has been set to 1 then write
a 0 in this bit.
(Initial value)
This bit is set to 1 when TCNT = TCORB.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6: CMFA
0
1
Description
To clear CMFA, the CPU must read CMFA after it has been set to 1, then write
a 0 in this bit.
(Initial value)
This bit is set to 1 when TCNT = TCORA.
Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 5: OVF
0
1
Description
To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0
in this bit.
(Initial value)
This bit is set to 1 when TCNT changes from H'FF to H'00.
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