HD64F3437TF16 Datasheet, PDF (312/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Section 13 I²C Bus Interface [Option]
An I²C bus interface is available as an option. Observe the following notes when using this option.
For mask-ROM versions, products that use this option have a “W” added to the product number.
Examples: HD6433437WTF, HD6433434WF
13.1 Overview
The I²C bus interface conforms to and provides a subset of the Philips I²C bus (inter-IC bus)
interface functions. The register configuration that controls the I²C bus differs partly from the
Philips configuration, however.
The I²C bus interface uses only one data line (SDA) and one clock line (SCL) to transfer data, so it
can save board and connector space. Figure 13.1 shows typical I²C bus interface connections.
13.1.1 Features
• Conforms to Philips I²C bus interface
• Start and stop conditions generated automatically
• Selectable acknowledge output level when receiving
• Auto-loading of acknowledge bit when transmitting
• Selection of eight internal clocks (in master mode)
• Selection of acknowledgement mode, or serial mode without acknowledge bit
• Wait function: A wait can be inserted in acknowledgement mode by holding the SCL pin low
after a data transfer, before acknowledgement of the transfer.
• Three interrupt sources
 Data transfer end
 In slave receive mode: slave address matched, or general call address received
 In master transmit mode: bus arbitration lost
• Direct bus drive (pins SCL and SDA)
• In addition to pins SCL and SCA, four general port pins (PA₄ to PA₇) can also drive the bus
• Pins P8₆/SCK₁/SCL, P9₇/WAIT/SDA, and PA₄/KEYIN₁₂ to PA₇/KEYIN₁₅ (total of 6 pins) are
all powered by bus power supply V_CCB, separate from V_CC. When the bus drive function is
selected, all output is NMOS output.
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