HD64F3437TF16 Datasheet, PDF (607/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Item
Test
Symbol Min
Typ
Max Unit Condition
Erase
Wait time after x
SWE-bit setting^*1
10
—
—
µs
Wait time after y
ESU-bit setting^*1
200
—
—
µs
Wait time after z
E-bit setting^{*1, *6}
5
—
10
ms
Wait time after α
E-bit clear^*1
10
—
—
µs
Wait time after β
ESU-bit clear^*1
10
—
—
µs
Wait time after γ
EV-bit setting^*1
20
—
—
µs
Wait time after ε
dummy write^*1
2
—
—
µs
Wait time after η
5
—
—
µs
EV-bit clear^*1
Maximum erase N
count^{*1, *6, *7}
—
—
120
Times tE = 10 ms
Notes: *1 Set the times according to the program/erase algorithms.
*2 Programming time per 32 bytes (Shows the total period for which the P-bit in FLMCR1
is set. It does not include the programming verification time.)
*3 Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does
not include the erase verification time.)
*4 Maximum programming time (tP (max) = wait time after P-bit setting (z) × maximum
programming count (N))
Set the wait time after P-bit setting (z) to the minimum value of 150 µs when the write
counter in the 32-byte write algorithm is between 1 and 4.
*5 Number of times when the wait time after P-bit setting (z) = 150 µs or 500 µs.
The number of writes should be set according to the actual set value of (z) to allow
programming within the maximum programming time (tP).
*6 Maximum erase time (tE (max) = Wait time after E-bit setting (z) × maximum erase
count (N))
*7 Number of times when the wait time after E-bit setting (z) = 10 ms.
The number of erases should be set according to the actual set value of z to allow
erasing within the maximum erase time (tE).
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