HD64F3437TF16 Datasheet, PDF (230/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

9.3.2 Compare-Match Timing
Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are
set to 1 by an internal compare-match signal generated when the timer count matches the time
constant in TCORA or TCORB. The compare-match signal is generated at the last state in which
the match is true, just before the timer counter increments to a new value.
Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 9.4 shows the timing of the setting
of the compare-match flags.
ø
TCNT
N
N+1
TCOR
N
Internal compare-
match signal
CMF
Figure 9.4 Setting of Compare-Match Flags
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