HD64F3437TF16 Datasheet, PDF (333/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

13.3.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The receive procedure and operations in slave receive
mode are described below. See also figure 13.9.
1. Set bits MLS and WAIT in ICMR and bits MST, TRS, and ACK in ICCR according to the
operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode.
2. A start condition output by the master device sets BBSY to 1 in ICSR.
3. After the slave device detects the start condition, if the first byte matches its slave address, at
the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the
same time, IRIC is set to 1 in ICSR. If IEIC is 1 in ICCR, a CPU interrupt is requested. The
slave device holds SCL low from the fall of the receive clock until it has read the data in
ICDR.
4. Software clears IRIC to 0 in ICSR.
5. When ICDR is read, receiving of the next data starts.
Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a
low-to-high transition of SDA while SCL is high), BBSY is cleared to 0 in ICSR.
SCL (master
output)
SCL (slave
output)
SDA (master
output
Start condition
1 23 45 67 89
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
Bit 7
SDA (slave
output)
IRIC
A
Interrupt
request
User processing
304
4. Clear IRIC
Figure 13.9 Timing in Slave Receive Mode
(MLS = WAIT = ACK = ACKB = 0)
5. Read ICDR