HD64F3437TF16 Datasheet, PDF (110/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt
becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR
or MOV instruction, for example, and the interrupt is requested during execution of that
instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution
of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a
higher-priority interrupt is requested at the same time, however, the hardware exception-handling
sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to 0.
Figure 4.8 shows an example in which the OCIAE bit is cleared to 0.
ø
Internal address bus
CPU write
cycle to TIER
OCIA interrupt handling
TIER address
Internal write signal
OCIAE
OCFA
OCIA interrupt signal
Figure 4.8 Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt
mask bit (I) is set to 1.
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